The invention relates to a circuit arrangement for converting a digital input signal into an analog output signal, comprising a voltage divider chain which, arranged between its ends which are fed by at least one reference voltage source, has a plurality of taps which, under the control of the digital input signal are connectable to an output for deriving the analog output signals.
The DE-OS No. 31 26 084, more specifically FIG. 3 with its associated description, discloses a digital-to-analog converter in which a plurality of analog values are supplied by a voltage divider constituted by a series arrangement of a plurality of resistors. The sections of this voltage divider are each connected to an input electrode of a switching transistor assigned to it. The output electrodes of the switching transistors are all connected to the analog output. In addition, the converter comprises a plurality of NOR-gates of which there are as many as there are switching transistors and to whose inputs a digital input signal consisting of several parallel bits is applied. For each digital value of the digital input signal, only one of the NOR-gates produces an output value "1". The outputs of the NOR-gates are connected to the control electrodes of each of the switching transistors. Depending on the digital input signal applied, only one of the switching-transistors becomes conductive and the corresponding analog value occurs at the output.
Digital-to-analog converters of the above type are superior to other types of converters because of the high linearity of the converter characteristic and an analog signal which is free from interferences, more specifically from so-called glitches.
In the described circuit arrangement in accordance with the prior art, the analog output signal taken-off from the voltage divider is applied to the output via a switching transistor. These switching transistors have parasitic capacitances at their input and output electrodes, particularly with respect to the ground potential and also a finite contact resistance between their input and output electrodes. Particularly with the aimed-at integration of the whole circuit arrangement on a semiconductor wafer and the consequent small dimensions of the switching transistors, the contact resistances then get to be such high values that the analog output signal can only be conveyed in an extremely high resistive manner, to keep parasitic voltage drops below the limit of resolution of the analog output signal. In addition, the capacitances of the output electrodes form, together with the contact resistances, a low-pass filter arrangement which considerably limits the range of signal frequencies the circuit arrangement is capable of transmitting.